For the purposes of imaging a scene, at low ambient illumination levels using a focal plane array comprised of solid-state detector devices, it is beneficial for the individual detectors in the array to be sensitive to light over a broad wavelength range and at single photon intensity levels. To support the fabrication of such an array of highly sensitive solid-state light detectors over broad spectral range, the back-illuminated semiconductor wafer substrate on which the detector devices are fabricated should be capable of transmitting light into the detectors with high efficiency from the ultraviolet to the midwave infrared for enabling high quantum efficiency detectors. The back-illumination approach of semiconductor detectors through the transparent supporting wafer substrate is the preferred approach for fabricating large area, solid-state, imaging focal plane arrays due to a higher attainable quantum efficiency and sensitive-area-fill-factor for such detectors compared to front-illuminated detector arrays. Back-illuminated detector arrays can be flip-chip bump-bonded to CMOS readout integrated circuits (ROICs) that control detector operation. Using highly sensitive detector arrays of avalanche photodiodes (APDs) is the preferred approach for implementing compact, solid-state, single photon sensitive, focal plane array (FPA) imagers. The semiconductor wafer substrate should therefore support the light detecting elements to be fabricated with small pixel pitch for enabling high resolution arrays, by providing a means for optical crosstalk isolation between the APD detector elements. Optical crosstalk in solid-state avalanche detector arrays results from light emission during impact ionization that can erroneously trigger neighboring detector pixels in the array and increase the overall detector noise. In addition, the semiconductor wafer substrate should support a high quality single crystal active semiconductor material layer with low defect density, in which light detecting elements characterized by low dark current can be fabricated.
The present invention describes a method for implementing a very high transmittance, back-illuminated, silicon-on-sapphire semiconductor wafer substrate to support the fabrication of large scale, high quantum efficiency and high resolution silicon (Si) or silicon germanium (SiGe) avalanche photodiode focal plane array (APD-FPA) imagers. The very high transmittance silicon-on-sapphire substrate incorporates an antireflective bilayer comprised of refractive index matched single crystal aluminum nitride (AlN) in conjunction with amorphous, non-stoichiometric, silicon rich, silicon nitride (a-SiNX<1.33), designated as (AlN/a-SiNX<1.33), between the sapphire and silicon to improve the transmittance of light from sapphire into the silicon detector device layer. An amorphous, one quarter wavelength magnesium fluoride (λ/4-MgF2) antireflective layer deposited on the back surface of the thinned sapphire wafer is meant to provide refractive index matching and thereby improve the optical transmittance from the ambient into the sapphire. The single crystal AlN component of the antireflective bilayer can be grown by epitaxy in non-polar A-plane orientation on semipolar R-plane sapphire substrates or grown in polar C-plane orientation on lower cost C-plane sapphire substrates. The amorphous, non-stoichiometric a-SiNX<1.33 component of the antireflective bilayer can be deposited by low pressure chemical vapor deposition (LPCVD) for example, on a full thickness (100) silicon wafer substrate followed by wafer bonding of the non-stoichiometric a-SiNX<1.33 on (100) silicon, to the single crystal AlN-on-sapphire. The (100) silicon wafer can be subsequently thinned using lapping and polishing to an appropriate thickness for fabrication of detector devices.
Using non-stoichiometric a-SiNX<1.33 for the antireflective layer is necessary, to provide proper refractive index matching in conjunction with single crystal AlN, between the sapphire and silicon. The stoichiometric a-SiNX=1.33 or a-Si3N4 has a refractive index that is too low to provide adequate refractive index matching between the AlN and silicon. Moreover, non-stoichiometric, silicon-rich a-SiNX<1.33 has a lower tensile strain than stoichiometric a-SiNX=1.33 when deposited on silicon and this helps to reduce the injection of defects into the silicon device layer. In addition, although a-SiNX<1.33 is meant to function primarily as an antireflective layer in the present invention, it can also perform the important secondary function of passivating the (100) silicon surface and silicon bulk. If the a-SiNX<1.33 thin film layer is deposited at a sufficiently low temperature of 200-450° C. by plasma enhanced chemical vapor deposition (PECVD) or hot filament chemical vapor deposition (HFCVD) methods for example, and therefore still retains hydrogen from the gaseous precursor chemicals used for deposition, the hydrogen will diffuse out of the a-SiNX<1.33 layer and into the silicon to passivate the silicon surface and also the silicon semiconductor bulk defects.
The very high transmittance, back-illuminated silicon-(AlN/a-SiNX<1.33)-sapphire substrate with λ/4-MgF2 back-side antireflective layer, readily supports fabrication of silicon mesa detectors with exposed (111) side planes and fixed crystallographic angle φC=54.7° between (100) and (111) silicon planes, by liquid anisotropic etching using tetramethyl ammonium hydroxide (TMAH) to define the mesa APD detector array. The AlN/a-SiNX<1.33 antireflective bilayer and sapphire act as natural etch stopping layers to enable fabrication of highly uniform silicon mesa pixels by crystallographic etching. In addition, monolithic sapphire microlenses can be fabricated beneath each mesa APD detector pixel in the thinned sapphire to focus light under the full height of the detector mesas. The space between mesa APD detector pixels can be filled by an aluminum (Al) or copper (Cu) metal anode grid, forming a common anode electrical connection at the base of each silicon detector mesa. The Al metal common anode grid also performs the important secondary function of providing optical crosstalk isolation between adjacent APD detectors by blocking light emitted during the avalanche gain process.
In the relatively recent past, it has become possible to fabricate solid-state arrays of silicon avalanche photodiodes optimized to operate either in linear mode or in non-linear Geiger-mode and capable of providing single photon sensitivity over a wavelength range from ultraviolet (UV) to near infrared (NIR). Focal plane arrays comprised of such linear or Geiger-mode silicon APD detectors, however, have only been fabricated in less than optimal substrate material systems due to the unavailability of a fully optimized wafer substrate, inherently capable of supporting high broadband quantum efficiency and high resolution, back-illuminated detector arrays with monolithic microlenses and optical crosstalk isolation between adjacent pixels in the array. To date, no effective substrate technology exists that inherently provides nearly 100% broadband, back-illuminated optical transmittance into the silicon semiconductor detector device layer, while supporting small pixel pitch, high resolution APD detector arrays with monolithic microlenses and optical crosstalk isolation between adjacent pixels.
As illustrated in U.S. Pat. No. 7,271,376, the design of a silicon avalanche photodiode control circuit and detector device uses a silicon-on-insulator wafer where the starting substrate is described to be either the handle wafer of a p-silicon-on-insulator wafer or a p-Si substrate with a SiO2 insulating layer. This substrate design however, is not optimized to provide nearly 100% back-illuminated optical transmittance into the APD detector or to provide optical crosstalk isolation that will enable high resolution arrays.
As illustrated in U.S. Pat. No. 7,268,339, a method is described for forming semiconductor avalanche photodiodes in an n-doped semiconductor wafer using a plurality of doped, opposing trenches in the top and bottom surfaces of the substrate wafer. The substrate design is not optimized to provide nearly 100% back-illuminated optical transmittance into the APD detector or to provide optical crosstalk isolation that will enable high resolution arrays.
As illustrated in U.S. Pat. No. 6,864,965, the imaging focal plane array supports dual-mode operation in both passive and active detection modes using LADAR pulses for the active mode. Switching between detection modes is accomplished by increasing the voltage bias across the detector so as to increase the gain and therefore sensitivity to the active laser pulse returns from objects in a scene. The mercury-cadmium-telluride (HgCdTe) detector pixels are shown to be fabricated in a semiconductor substrate having an antireflective coating applied to the surface. This substrate design is not optimized to provide nearly 100% broadband, back-illuminated optical transmittance into the APD detector or to provide optical crosstalk isolation that will enable high resolution arrays.
In another embodiment of a position sensitive solid-state detector with internal gain, U.S. Pat. No. 6,781,133 B2, the invention describes a detection device and signal readout scheme, that uses an n-silicon substrate that is doped with p-materials using deep diffusion. This substrate design is not optimized to provide nearly 100% broadband, back-illuminated optical transmittance into the APD detector or to provide optical crosstalk isolation that will enable high resolution arrays.
In another embodiment, U.S. Pat. No. 5,892,575, a method and apparatus for imaging a scene are described for resolving the 3-D spatial structure in the scene. The light source emits pulses of laser light toward the object being imaged and the detector system includes an optical system and an array of light detectors operating in non-linear Geiger-mode. The optical system collects a portion of the light scattered off of objects in the scene and directs the collected light toward the array of light detectors. The invention refers to a monolithic array of light detectors operating in the non-linear Geiger-mode and does not describe an optimal substrate design for fabricating the Geiger-mode APD detectors that is capable of providing nearly 100% broadband, back-illuminated optical transmittance into the APD detectors or to provide optical crosstalk isolation that will enable high resolution arrays.
In another embodiment, U.S. Pat. No. 5,757,057, a method for fabricating a large array of avalanche photodiodes using a plurality of pixel contacts that are isolated electrically by one or more isolation structures is revealed. The avalanche photodiode pixels, however, are fabricated in a semiconductor substrate comprised of two oppositely doped layers and is not optimized to provide nearly 100% broadband, back-illuminated optical transmittance into the APD detectors or to provide optical crosstalk isolation that will enable high resolution arrays.
In another embodiment, U.S. Pat. No. 5,438,217, a planar avalanche photodiode device array is realized using a planar block of n-type semiconductor having a plurality of p-type wells in the block surrounded by a foundation of n-type semiconductor material. This substrate design is not optimized to provide nearly 100% broadband, back-illuminated optical transmittance into the APD detector or to provide optical crosstalk isolation that will enable high resolution arrays.
In another embodiment, U.S. Pat. No. 4,177,084, a method for producing a low defect layer of silicon on a sapphire substrate is provided. The silicon-on-sapphire (SOS) wafer is formed by epitaxial deposition of (100) silicon directly on the R-plane sapphire substrate followed by implanting of Si ions near the higher defect density silicon-sapphire interface. Subsequent annealing of the amorphised silicon near the sapphire surface using the low defect density silicon near the top of the epitaxial layer as a template for regrowth, produces an improved quality silicon device layer near the sapphire. The substrate fabrication approach, however, does not describe a method of providing nearly 100% broadband, back-illuminated optical transmittance through the sapphire substrate into the silicon semiconductor layer where APD detectors can be fabricated.
In another embodiment, U.S. Pat. No. 5,441,591, a method for fabricating a silicon-on-sapphire wafer is provided using direct wafer bonding of a silicon wafer to a sapphire wafer by application of pressure and elevated temperature. The full thickness silicon wafer is subsequently thinned by chemical mechanical polishing to an appropriate thickness for fabricating semiconductor devices. The substrate fabrication approach, however, does not describe a method of providing nearly 100% broadband, back-illuminated optical transmittance through the sapphire substrate into the silicon APD detector.
Note that the above solid-state, semiconductor, avalanche detectors and silicon-on-sapphire substrate fabrication approaches do not envision, nor describe a method for realizing an optimal substrate design for silicon APD-FPAs that provides nearly 100% broadband, back-illuminated optical transmittance into the APD detectors and provides an effective means for optical crosstalk isolation between detectors to enable high resolution arrays.